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lt3509 1 3509f typical application features applications description dual 36v, 700ma step-down regulator the lt ? 3509 is a dual, current mode, step-down switching regulator, with internal power switches each capable of providing 700ma output current. this regulator provides a compact and robust solution for multi-rail systems in harsh environments. it incorporates several protection features including overvoltage lockout and cycle by cycle current limit. thermal shutdown provides additional protection. the loop compensation components and the boost diodes are integrated on-chip. switching frequency is set by a single external resistor. external synchronization is also possible. the high maximum switching frequency allows the use of small inductors and ceramic capacitors for low ripple. constant frequency operation above the am band avoids interference with radio reception, making the lt3509 well suited for automotive applications. each regulator has an independent shutdown and soft-start control pin. when both converters are powered down, the common circuitry enters a low current shutdown state. 3.3v and 5v dual output step-down converter n two 700ma switching regulators with internal power switches n wide 3.6v to 36v operating range n over-voltage lockout protects circuit through 60v supply transients n short circuit robust n low dropout voltage ? 95% maximum duty cycle n adjustable 300khz to 2.2mhz switching frequency synchronizable over the full range n uses small inductors and ceramic capacitors n integrated boost diodes n internal compensation n thermally enhanced 14 lead (4 mm 3 mm) dfn and 16 lead msop packages n automotive electronics n industrial controls n wall transformer regulation n networking devices n cpu, dsp, or fpga power 3509 ta01a lt3509 gnd da1 fb1 run/ss1 sync da2 fb2 run/ss2 r t bd v in boost2 boost1 sw2 sw1 10h f sw = 700khz 0.1f 0.1f 6.5v to 36v (transient to 60v) 2.2f 6.8h 3.3v 700ma 5v 700ma 10f 10.2k 31.6k 53.6k mbrm140 mbrm140 1nf 22f 10.2k 60.4k 1nf load current (a) 0.0 efficiency (%) 70 75 80 0.7 3509 ta01b 60 65 50 55 0.1 0.2 0.6 90 85 0.5 0.4 0.3 v out = 3.3v v out = 5v v in = 12v f sw = C700khz ef? ciency l , lt, ltc and ltm are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners.
lt3509 2 3509f absolute maximum ratings v in pin (note 2) ........................................................60v bd pin .......................................................................20v boost pins ..............................................................60v boost pins above sw .............................................30v run/ss, fb, r t , sync pins ........................................6v (note 1) pin configuration order information lead free finish tape and reel part marking* package description temperature range lt3509ede#pbf lt3509ede#trpbf 3509 14-lead (4mm 3mm) plastic dfn ?40c to 125c lt3509ide#pbf lt3509ide#trpbf 3509 14-lead (4mm 3mm) plastic dfn ?40c to 125c lt3509emse#pbf lt3509emse#trpbf 3509 16-lead plastic msop with exposed pad ?40c to 125c lt3509imse#pbf lt3509imse#trpbf 3509 16-lead plastic msop with exposed pad ?40c to 125c consult ltc marketing for parts speci? ed with wider operating temperature ranges. *the temperature grade is identi? ed by a label on the shipping container. consult ltc marketing for information on non-standard lead based ? nish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/ operating junction temperature range (notes 3, 5) lt3509e ............................................. ?40c to 125c lt3509i .............................................. ?40c to 125c storage temperature range ................... ?65c to 150c lead temperature (soldering, 10 sec.) mse16 package ................................................ 300c 1 2 3 4 5 6 7 14 13 12 11 10 9 8 fb1 run/ss1 bd sync r t run/ss2 fb2 da1 boost1 sw1 v in sw2 boost2 da2 top view de14 package 14-lead (4mm s 3mm) plastic dfn 15 ja = 43c/w, jc = 4.3c/w exposed pad (pin 15) is gnd, must be soldered to pcb 1 2 3 4 5 6 7 8 da1 boost1 sw1 v in v in sw2 boost2 da2 16 15 14 13 12 11 10 9 fb1 run/ss1 agnd bd sync r t run/ss2 fb2 top view mse package 16-lead plastic msop 17 ja = 43c/w, jc = 4.3c/w exposed pad (pin 17) is gnd, must be soldered to pcb
lt3509 3 3509f electrical characteristics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2 . absolute maximum voltage at the v in pin is 60v for non-repetitive 1 second transients and 36v for continuous operation. note 3. the lt3509e is guaranteed to meet performance speci? cations from 0c to 125c junction temperature. speci? cations over the C40c to 125c operating junction temperature range are assured by design, characterization the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c, v in = 12v, v bd = 5v. (note 3) parameter conditions min typ max units v in undervoltage lockout 3.3 3.6 v v in overvoltage lockout 37 38.5 40 v input quiescent current not switching v fb > 0.8v 1.9 2.2 ma input shutdown current v(run/ss[1,2]) < 0.3v 9 15 a feedback pin voltage l 0.784 0.8 0.816 v reference voltage line regulation 3.6v < v in < 36v 0.01 %/v run/ss shutdown threshold 0.4 0.6 0.8 v run/ss voltage for full i out 2v run/ss pin pull-up current 0.7 1 1.3 a feedback pin bias current l 90 500 na switch current limit l 1.05 1.4 1.9 a da comparator current threshold 0.7 0.95 1.2 a boost pin current i sw = 0.9a 22 36 ma switch leakage current 0.01 1.0 a switch saturation voltage i sw = 0.9a (note 4) 0.32 v minumum boost voltage above switch i sw = 0.9a 1.5 2.2 v boost diode forward voltage i bd = 20ma 0.7 0.9 v boost diode leakage v r = 30v 0.1 5 a switching frequency r t = 40.2k r t = 180k r t = 14.1k l 0.92 237 2.0 1.0 264 2.2 1.08 290 2.5 mhz khz mhz switch minimum off time l 80 150 ns and correlation with statistical process controls. the lt3509i is guaranteed over the full C40c to 125c temperature range. note 4 . switch saturation voltage is guaranteed by design. note 5. this ic includes over-temperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed the maximum operating temperature when overtemperature protection is active. continuous operation above the speci? ed maximum operating junction temperature may impair device reliability.
lt3509 4 3509f typical performance characteristics i load (a) 0 efficiency (%) 0.8 3509 g01 65 70 75 80 85 90 60 0.2 0.4 0.6 95 v in = 12v t a = 25oc v in = 24v i load (a) 0 efficiency (%) 0.8 3509 g02 60 65 70 75 80 85 90 55 0.2 0.4 0.6 95 v in = 12v t a = 25oc i load (a) 0 efficiency (%) 0.8 3509 g03 55 60 65 70 75 80 85 50 0.2 0.4 0.6 90 v in = 12v t a = 25oc i sw (a) 0 v ce(sat) (v) 1.0 0.8 3509 g04 0.05 0.1 0.15 0.2 0.25 0.3 0 0.2 0.4 0.6 0.35 t a = 25oc i sw (a) 0 i boost (ma) 0.8 1 3509 g05 5 10 15 20 0 0.2 0.4 0.6 25 t a = 25oc boost diode current (ma) 0 v f (v) 100 150 3509 g06 0.2 0.4 0.6 0.8 1 0 50 1.2 t a = 25oc r t (k) 0 frequency (mhz) 120 140 100 160 180 3509 g07 0.5 1.0 1.5 2.0 2.2 0 60 80 20 40 t a = 25oc ef? ciency vs load current v out = 5v, f sw = 2.0mhz ef? ciency vs load current v out = 3.3v, f sw = 2.0mhz ef? ciency vs load current v out = 1.8v, f sw = 0.7mhz switch v ce(sat) vs i sw i boost vs i sw boost diode characteristics frequency vs r t
lt3509 5 3509f temperature(oc) ?50 f sw (mhz) 100 125 75 3509 g08 0.98 0.985 0.99 0.995 1 1.005 1.01 1.015 1.02 1.025 0.975 25 50 ?25 0 r t = 40.2k ?50 100 125 75 25 50 ?25 0 fbref (v) 3509 g09 0.795 0.8 0.805 0.81 0.79 temperature(oc) f sw vs temperature fb pin voltage vs. temperature typical performance characteristics i load (a) 0 maximum v in (v) 0.6 0.4 0.8 3509 g10 5 10 15 20 25 0 0.2 30 t a = 25oc t a = 85oc i load (a) 0 maximum v in (v) 3509 g11 5 10 15 20 25 0 45 30 35 40 t a = 25oc t a = 85oc 0.6 0.4 0.8 0.2 minimum on time (ns) 3509 g12 20 40 60 80 100 120 0 140 ?50 100 125 75 25 50 ?25 0 temperature(oc) max v in for constant frequency v out = 3.3v, f sw = 2mhz max v in for constant frequency v out = 5v, f sw = 2mhz min on time vs. temperature i load = 0.3a temperature (oc) 40 i lim (a) 120 3509 g13 0.5 1 1.5 0 0 40 80 2 da switch duty cycle (%) 010 i lim (a) 100 3509 g14 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 0 20 30 40 50 60 70 80 90 1.8 t a = 25oc i lim vs temperature i lim vs duty cycle
lt3509 6 3509f pin functions da1, da2 (pins 1, 7 / pins 1, 8): the da pins are the anode connections for the catch diodes. these are con- nected internally to the exposed ground pad by current sensing resistors. boost1, boost2 (pins 2, 6 / pins 2, 7): the boost pins are used to dynamically boost the power transistor base above v in to minimize the voltage drop and power loss in the switch. these should be tied to the associated switch pins through the boost capacitors. sw1, sw2 (pins 3, 5 / pins 3, 6): the sw pins are the internal power switch outputs. these should be connected to the associated inductors, catch diode cathodes, and the boost capacitors. v in (pin 4 / pins 4, 5): the v in pins supply power to the internal power switches and control circuitry. in the mse package the v in pins must be tied together. the input capacitor should be placed as close as possible to the supply pins. fb1, fb2 (pins 14, 8 / pins 16, 9): the fb pins are used to set the regulated output voltage relative to the internal reference. these pins should be connected to a resistor divider from the regulated output such that the fb pin is at 0.8v when the output is at the desired voltage. run/ss1, run/ss2 (pins 13, 9 / pins 15, 10): the run/ss pins enable the associated regulator channel. if both pins are pulled to ground, the device will shut-down to a low power state. in the range 0.7v to 2.0v, the regulators are enabled but the peak switch current and the da pin maxi- mum current are limited to provide a soft-start function. above 2v, the full output current is available. the inputs incorporate a 1a pull-up so that they will ? oat high or charge an external capacitor to provide a current limited soft-start. the pins are pulled down by approximately 250a in the case of overvoltage or overtemperature conditions in order to discharge the soft-start capacitors. the pins can also be driven by a logic control signal of up to 5.0v. in this case, it is necessary place a 10k to 50k resistor in series along with a capacitor from the run/ss pin to ground to ensure that there will be a soft-start for both initial turn on and in the case of fault conditions. do not tie these pins to v in . r t (pin 10 / pin 11): the r t pin is used to set the internal oscillator frequency. a 40.2k resistor from r t to ground results in a nominal frequncy of 1mhz. sync (pin 11 / pin12): the sync pin allows the switching frequency to be synchronized to a external clock. choose r t resistor to set a free-run frequency at least 12% less than the external clock frequency for correct operation. bd (pin 12 / pin 13): the bd pin is common anode con- nection of the internal schottky boost diodes. this provides the power for charging the boost capacitors. it should be locally bypassed for best performance. gnd (exposed pad): this is the reference and supply ground for the regulator. the exposed pad must be soldered to the pcb and electrically connected to supply ground. use a large ground plane and thermal vias to optimize thermal performance. the current in the catch diodes also ? ows through the gnd pad to the da pins. agnd (pin 14, mse package only): this is the connected to the ground connection of the chip and may be used as a separate return for the low current control side components. it should not be used as the only ground connection or as a connection return for load side components. (dfn/mse)
lt3509 7 3509f block diagram shutdown and soft-start control overvoltage detect common circuitry 1 of 2 regulator channels shown switch logic clamp C17mv 18m 7 gnd bd v ref 0.8v switch driver error amplifier da current comparator l1 d1 r1 r2 main current comparator power switch boost diode boost sw da c5 fb v c slope r t r t sync c3 c4 c1 run/ss2 run/ss1 v in v out v ref and core voltage regulator oscillator 3509 bd c2 note: the bd pin is common to both channels. figure 1. functional block diagram
lt3509 8 3509f operation overview the lt3509 is a dual, constant frequency, current mode switching regulator with internal power switches. the two independent channels share a common voltage reference and oscillator and operate in phase. the switching frequency is set by a single resistor and can also be synchronized to an external clock. operation can be best understood by referring to the block diagram (figure 1). startup and shutdown when the run/ss[1,2] pins are pulled low (<0.3v) the associated regulator channel is shut-down. if both channels are shut down, the common circuitry also enters a low current state. when the run/ss pins exceed approximately 0.7v, the common circuitry and the associated regulator are enabled but the output current is limited. from 0.7v up to 2.0v the current limit increases until it reaches the full value. the run/ss pins also incorporate a 1a pull-up to approximately 3v, so the regulator will run if they are left open. a capacitor to ground will cause a current limited soft-start to occur at power-up. in the case of undervoltage, overvoltage or over-temperature conditions the internal circuitry will pull the run/ss pins down with a current of approximately 250a. thus a new soft-start cycle will occur when the fault condition ends. voltage and current regulation the power switches are controlled by a current-mode regulator architecture. the power switch is turned on at the beginning of each clock cycle and turned off by the main current comparator. the inductor current will ramp up while the switch is on until it reaches the peak current threshold. the current at which it turns off is determined by the error amp and the internal compensation network. when the switch turns off, the current in the inductor will cause the sw pin to fall rapidly until the catch diode, d1, conducts. the voltage applied to the inductor will now reverse and the current will linearly fall. the resistor divider, r1 and r2, sets the desired output voltage such that when the voltage at fb reaches 0.8v, the main current comparator threshold will fall and reduce the peak inductor current and hence the average current, until it matches the load current. by making current the controlled variable in the loop, the inductor impedance is effectively removed from the transfer function and the compensation network is simpli? ed. the main current comparator threshold is reduced by the slope compensation signal to eliminate sub-harmonic oscillations at duty cycles >50%. current limiting current mode control provides cycle by cycle current limiting by means of a clamp on the maximum current that can be provided by the switch. a comparator monitors the current ? owing through the catch diode via the da pin. this comparator delays switching if the diode current is higher than 0.95a (typical). this current level is indicative of a fault condition such as a shorted output with a high input voltage. switching will only resume once the diode current has fallen below the 0.95a limit. this way the da comparator regulates the valley current of the inductor to 0.95a during a short circuit. this will ensure the part will survive a short circuit event. over and under voltage shutdown a basic under voltage lockout prevents switching if v in is below 3.3v (typical). the overvoltage shutdown stops the part from switching when v in is greater than 38.5v (typical). this protects the device and its load during momentary overvoltage events. after the input voltage falls below 38.5v, the part initiates a soft start sequence and resumes switching. boost circuit to ensure best ef? ciency and minimum dropout voltage the output transistor base drive is boosted above v in by the external boost capacitors (c4). when the sw pin is low the capacitors are charged via the boost diodes and the supply on bd.
lt3509 9 3509f applications information shutdown and soft start when the run/ss pins are pulled to ground, the part will shut down to its lowest current state of approximately 10a. if driving a large capacitive load it may be desirable to use the current limiting soft start feature. connecting capacitors to ground from the run/ss pins will control the delay until full current is available. the pull-up current is 1a and the full current threshold is 2v so the start-up time is given by: t = 2 c 10 6 s for example a 0.005f capacitor will give a time to full current of 10ms. if both outputs can come up together then the two inputs can be paralleled and tied to one ca- pacitor. in this case use twice the capacitor value to obtain the same start-up time. during the soft-start time both the peak current threshold and the da current threshold will track so the part will skip pulses as required to limit the maximum inductor current. starting up into a large capacitor is not much different to starting into a short- circuit in this respect. setting the output voltage the output voltage is programmed with a resistor divider between the output and the fb pin. choose the resistors according to: rr v out 12 0 8 1 = ? ? ? ? ? ? the designators correspond to figure 1. r2 should be 20k or less to avoid bias current errors. frequency setting the timing resistor r t for any desired frequency in the range 270khz to 2.2mhz can be calculated from the following formula: r f t sw = ? ? ? ? ? ? where f sw is in mhz and r t is in k. table 1. standard e96 resistors for common frequencies frequency timing resistor r t (k) 270 khz 165 300 khz 150 400khz 113 500khz 88.7 1mhz 40.2 2mhz 16.2 2.2mhz 14 figure 2. soft-start i l 0.2a/div v sw 10v/div v out 5v/div time 1ms/div 3509 f02
lt3509 10 3509f applications information external synchronization the external synchronization provides a trigger to the internal oscillator. as such, it can only raise the frequency above the free-run value. to allow for device and component tolerances, the free run frequency should be set to at least 12% lower than the lowest supplied external synchronization reference. the oscillator and hence the switching frequency can then pushed up from 12% above the free-run frequency, set by the selected r t . for example, if the minimum external clock is 300khz, the r t should be chosen for 264khz. the sync input has a threshold of 1.0v nominal so it is compatible with most logic levels. the duty cycle is not critical provided the high or low pulse width is at least 80ns. design procedure before starting detailed design a number of key design parameters should be established as these may affect design decisions and component choices along the way. one of the main things to determine apart from the desired output voltages is the input voltage range. both the normal operating range and the extreme conditions of surges and/or dips or brown-outs need to be known. then the operating frequency should be considered and if there are particular requirements to avoid interference. if there are very speci? c frequencies that need to be avoided then external synchronization may be needed. this could also be desirable if multiple switchers are used as low frequency beating between similar devices can be undesirable. for ef? cient operation this converter requires a boost supply so that the base of the output transistor can be pumped above the input voltage during the switch on time. depending on the input and output voltages the boost supply can be provided by the input voltage, one of the regulated outputs or an independent supply such as an ldo. input voltage range firstly, the lt3509 imposes some hard limits due to the undervoltage lock-out and the overvoltage protection. a given application will also have a reduced, normal operating range over which maximum ef? ciency and lowest ripple are obtained. this usually requires that the device is operating at a ? xed frequency without skipping pulses. there may also be zones above and below the normal range where regulation is maintained but ef? ciency and ripple may be compromised. at the low end, insuf? cient input voltage will cause loss of regulation and increased rippleCthis is the dropout range. at the high end if the duty cycle becomes too low this will cause pulse skipping and excessive ripple. this is the pulse-skip region. both situations also lead to higher noise at frequencies other than the chosen switching frequency. occasional excursions into pulse-skip mode, during surges for example, may be tolerable. pulse skipping will also occur at light loads even within the normal operating range but ripple is usually not degraded because at light load the output capacitor can hold the voltage steady between pulses. to ensure the regulator is operating in continuous mode it is necessary to calculate the duty cycle for the required output voltage over the full input voltage range. this must then be compared with minimum and maximum practical duty cycles.
lt3509 11 3509f applications information in any step-down switcher the duty cycle when operating in continuous, or ? xed frequency, mode is dependent on the step-down ratio. this is because for a constant average load current the decay of the inductor current when the switch is off must match the increase in inductor current when the switch is on. the can be estimated by the following formula: dc vv vv v out f in sw f = + ?+ where: dc = duty cycle (fraction of cycle when switch is on) v out = output voltage v in = input voltage v f = catch diode forward voltage v sw = switch voltage drop note: this formula neglects switching and inductor losses so in practice the duty cycle may be slightly higher. it is clear from this equation that the duty cycle will approach 100% as the input voltage is reduced and become smaller as the input voltage increases. there are practical limits to the minimum and maximum duty cycles for continuous operation due to the switch minimum off and on times. these are independent of operating frequency so it is clear that range of usable duty cycle is inverserly proportional to frequency. therefore at higher frequency the input voltage range (for constant frequncy operation) will narrow. the minimum duty cycle is given by: dc f t min sw on min = where: f sw = switching frequency t minon = switch minimum on time the minimum on time increases with increasing tempera- ture so the value for the maximum operating temperature should be used. see the minimum on time vs load graph in the typical performance characteristics. the maximum input voltage for this duty cycle is given by: v vv dc vv in max out f min fsw () = + ?+ above this voltage the only way the lt3509 can maintain regulation is to skip cycles so the effective freqeuncy will reduce. this will cause an increase in ripple and the switch- ing noise will shift to a lower frequency. this calculation will in practice drive the maximum switching frequency for a desired step-down ratio. figure 3. continuous mode i l 0.5a/div v out 100mv/div (ac coupled) time 1s/div 3509 f03 figure 4. pulse skipping i l 0.5a/div v out 100mv/div (ac coupled) time 1s/div 3509 f04
lt3509 12 3509f applications information minimum input voltage and boost architecture the minimum operating voltage is determined either by the lt3509s internal undervoltage lockout of ~3.6v or by its maximum duty cycle. the maximum duty cycle for ? xed frequency operation is given by: dc t f max off min sw =? it follows that: v vv dc vv in min out f max fsw () = + ?+ if a reduction in switching frequency can be tolerated the minimum input voltage can drop to just above output voltage. not only is the output transistor base pumped above the input voltage by the boost capacitor, the switch can remain on through multiple switching cycles resulting in a high effective duty cycle. thus, this is a true low-dropout regulator. as it is necessary to recharge the boost capacitor from time to time, a minimum width off-cycle will be forced occasionally to maintain the charge. depending on the operating frequency, the duty cycle can reach 97-98%, although at this point the output pulses will be at a sub-multiple of the programmed frequency. one other consideration is that at very light loads or no load the part will go into pulse skipping mode. the part will then have trouble getting enough voltage on to the boost capacitors to fully saturate the switch. this is most problematic when the bd pin is supplied from the regulated output. the net result is that a higher input voltage will be required to start up the boost system. the typical minimum input voltage over a range of loads is shown in figure 5 for 3.3v and figure 6 for 5.0v. when operating at such high duty cycles the peak currents in the boost diodes are greater and this will require a the bd supply to be somewhat higher than would be required at less extreme duty cycles. if operation at low input/output ratios and low bd supply voltages is required it may be desirable to augment the internal boost diodes with external discrete diodes in parallel. boost pin considerations the boost capacitor, in conjunction with the internal boost diode, provides a bootstrapped supply for the power switch that is above the input voltage. for operation at 1mhz and above and at reasonable duty cycles a 0.1f capacitor will work well. for operation at lower frequencies and/or higher duty cycles something larger may be needed. a good rule of thumb is: v vv dc vv in min out f max fsw () = + ?+ where f sw is in mhz and c boost is in f figure 5. minimum v in for 3.3v v out load current (a) 0.001 v in to start (v) 4 4.5 5 1 3509 f05 3 3.5 2.5 2 0.01 0.1 5.5 to start to run figure 6. minimum v in for 5.0v v out load current (a) 0.001 v in to start (v) 6 6.5 1 3509 f06 5 5.5 4.5 4 0.01 0.1 7 to start to run
lt3509 13 3509f applications information figure 7. bd tied to regulated output l1 d1 c out v out c boost v boost Cv sw v out max v boost v in v out v out r 3v v in 3509 f07 lt3509 gnd v in bd boost sw da c in boost pin considerations figure 7 through figure 9 show several ways to arrange the boost circuit. the boost pin must be more than 2.0v above the sw pin for full ef? ciency. for outputs of 3.3v and higher, the standard circuit figure 7 is best. for lower output voltages, the boost diode can be tied to the input figure 8. the circuit in figure 7 is more ef? cient because the boost pin current comes from a lower voltage source. finally, as shown in figure 9, the bd pin can be tied to another source that is at least 3v. for example, if you are generating 3.3v and 1.8v, and the 3.3v is on whenever the 1.8v is on, the 1.8v boost diode can be connected to the 3.3v output. in any case, be sure that the maximum voltage at the boost pin is less than 60v and the voltage difference between the boost and sw pins is less than 30v. inductor selection and maximum output current a good ? rst choice for the inductor value is: lv v mhz f out f sw =+ where v f is the voltage drop of the catch diode (~0.5v) and l is in h. the inductors rms current rating must be greater than the maximum load current and its saturation current should be at least 30% higher. for highest ef? ciency, the series resistance (dcr) should be less than 0.15. table 2 lists several vendors and types that are suitable. the current in the inductor is a triangle wave with an average value equal to the load current. the peak switch current is equal to the output current plus half the peak-to-peak inductor ripple current. the lt3509 limits its switch current in order to protect itself and the system from over-current faults. therefore, the maximum output current that the lt3509 will deliver depends on the switch current limit, the inductor value and the input and output voltages. l1 d1 c out v out c boost v boost Cv sw v in max v boost 2v in c in v in 3509 f08 lt3509 gnd v in bd boost sw da figure 8. supplied from v in l1 d1 c out v out c boost v boost Cv sw v bd max v boost v in v bd v bd r 3v c in v in v bd 3509 f09 lt3509 gnd v in bd boost sw da figure 9. separate boost supply
lt3509 14 3509f when the switch is off, the potential across the inductor is the output voltage plus the catch diode forward voltage. this gives the peak-to-peak ripple current in the inductor: = + where: dc = duty cycle f sw = switching frequency l = inductor value v f = diode forward voltage. the peak inductor and switch current is: iii i swpk lpk out l ==+ to maintain output regulation, this peak current must be less than the lt3509s switch current limit i lim . this is dependent on duty cycle due to the slope compensation. for i lim is at least 1.4a at low duty cycles and decreases linearly to 1.0a at dc = 0.8. the theoretical minimum inductance can now be calcu- lated as: l dc f vv ii min min out f lim out = + where dc min is the minimum duty cycle called for by the application i.e. dc vv vvv min out max f in min sw f = + + there is a limit to the actual minimum duty cycle imposed by the minimum on time of the switch. for a robust design it is important that inductor that will not saturate when the switch is at its minimum on time, the input voltage is at maximum and the output is short-circuited. in this case the full input voltage, less the drop in the switch, will appear across the inductor. this doesnt require an actual short, just starting into a capacitive load will provide the same conditions. the diode current sensing scheme will ensure that the switch will not turn-on if the inductor current is above the da current limit threshold, which has a maximum of 1.1a. the peak current under short-circuit conditions can then be calculated from: i vt l a peak in on min =+ the inductor should have a saturation current greater than this value. for safe operation with high input voltages this can often mean using a physically larger inductor as higher value inductors often have lower saturation currents for a given core size. as a general rule the saturation current should be at least 1.8a to be short-circuit proof. however, its generally better to use an inductor larger than the minimum value. the minimum inductor has large ripple currents which increase core losses and require large output capacitors to keep output voltage ripple low. select an inductor greater than l min that keeps the ripple current below 30% of ilim. applications information
lt3509 15 3509f applications information table 2. recommended inductors manufacturer/ part number value (h) isat (a) dcr ( ) height (mm) coilcraft lps4018-222ml 2.2 2.8 0.07 1.7 lps5030-332ml 3.3 2.5 0.066 2.9 lps5030-472ml 4.7 2.5 0.083 2.9 lps6225-682ml 6.8 2.7 0.095 2.4 lps6225-103ml 10 2.1 0.105 2.4 sumida cdrh4d22/hp-2r2n 2.2 3.2 0.0035 2.4 cdrh4d22/hp-3r5n 3.5 2.5 0.052 2.4 cdrh4d22/hp-4r7n 4.7 2.2 0.066 2.4 cdrh5d28/hp-6r8n 6.8 3.1 0.049 3.0 cdrh5d28/hp-8r2n 8.2 2.7 0.071 3.0 cdrh5d28r/hp-100n 10 2.45 0.074 3.0 cooper sd52-2r2-r 2.2 2.30 0.0385 2.0 sd52-3r5-r 3.5 1.82 0.0503 2.0 sd52-4r7-r 4.7 1.64 0.0568 2.0 sd6030-5r8-r 5.8 1.8 0.045 3.0 sd7030-8r0-r 8.0 1.85 0.058 3.0 sd7030-100-r 10.0 1.7 0.065 3.0 toko a997as-2r2n 2.2 1.6 0.06 1.8 a997as-3r3n 3.3 1.2 0.07 1.8 a997as-4r7m 4.7 1.07 0.1 1.8 wrth 7447745022 2.2 3.5 0.036 2.0 7447745033 3.3 3.0 0.045 2.0 7447745047 4.7 2.4 0.057 2.0 7447745076 7.6 1.8 0.095 2.0 7447445100 10 1.6 0.12 2.0 the prior analysis is valid for continuous mode operation (i out > i lim / 2). for details of maximum output current in discontinuous mode operation, see linear technologys application note an44. finally, for duty cycles greater than 50% (v out /v in > 0.5), a minimum inductance is required to avoid subharmonic oscillations. this minimum inductance is lvv f min out f sw =+ where f sw is in mhz and l min is in h. if using external synchronization, calculate l min using the r t frequency and not the sync frequency. frequency compensation the lt3509 uses current mode control to regulate the output, which simpli? es loop compensation and allows the necessary ? lter components to be integrated. the ? xed internal compensation network has been chosen to give stable operation over a wide range of operating conditions but assumes a minimum load capacitance. the lt3509 does not depend on the esr of the output capacitor for stability so the designer is free to use ceramic capacitors to achieve low output ripple and small pcb footprint. figure 10 shows an equivalent circuit for the lt3509 control loop. the error amp is a transconductance ampli? er with ? nite output impedance. the power section, consisting of the modulator, power switch and inductor is modeled as a transconductance ampli? er generating an output current proportional to the voltage at the comp-node. the gain of the power stage (gmp) is 1.1s. note that the output capacitor integrates this current and that the internal capacitor integrates the error ampli? er output current, resulting in two poles in the loop. in most cases, a zero is required and comes either from the output capacitor esr
lt3509 16 3509f for ceramic capacitors where low capacitance value is more signi? cant than esr: vifc ripple l sw out = 8 for electrolytic capacitors where esr is high relative to capacitive reactance: v i esr ripple l = where i l is the peak-to-peak ripple current in the inductor. the rms content of this ripple is very low so the rms current rating of the output capacitor is usually not of concern. it can be estimated with the formula: ii crms l () / = another constraint on the output capacitor is that it must have greater energy storage than the inductor; if the stored energy in the inductor transfers to the output, the resulting voltage step should be small compared to the regulation voltage. for a 5% overshoot, this requirement indicates: cliv out lim out > the low esr and small size of ceramic capacitors make them the preferred type for lt3509 applications. not all ceramic capacitors are the same, however. many of the higher value capacitors use poor dielectrics with high temperature and voltage coef? cients. in particular, y5v and z5u types lose a large fraction of their capacitance with applied voltage and at temperature extremes. because loop stability and transient response depend on the value of c out , this loss may be unacceptable. use x7r and x5r types. applications information 75k r c comp- node r1 r2 1.73m 95pf v in v ref = 0.8v c pl 260s lt3509 1.1s v out 3509 f10 + c out figure 10. small signal equivalent circuit or from r c . this model works well as long as the inductor current ripple is not too low ( i ripple > 5% i out ) and the loop crossover frequency is less than f sw /5. an optional phase lead capacitor (cpl) across the feedback divider may improve the transient response. output capacitor selection the output capacitor ? lters the inductor current to generate an output with low voltage ripple. it also stores energy in order to satisfy transient loads and stabilize the lt3509s control loop. because the lt3509 operates at a high frequency, minimal output capacitance is necessary. in addition, the control loop operates well with or without the presence of output capacitor series resistance (esr). ceramic capacitors, which achieve very low output ripple and small circuit size, are therefore an option. you can estimate output ripple with the following equations:
lt3509 17 3509f the value of the output capacitor greatly affects the transient response to a load step. it has to supply extra current demand or absorb excess current delivery until the feedback loop can respond. the loop response is dependent on the error ampli? er transconductance, the internal compensation capacitor and the feedback net- work. higher output voltages necessarily require a larger feedback divider ratio. this will also reduce the loop gain and slow the response time. fortunately this effect can be mitigated by use of a feed-forward capacitor c pl across the top feedback resistor. the small signal model shown in figure 10 can be used to model this in a simulator or to give insight to an empirical design. figure 11 shows some load step responses with differing output capacitors and c pl combinations. input capacitor the input capacitor needs to supply the pulses of charge demanded during the on time of the switches. little total capacitance is required as a few hundred millivolts of ripple at the v in pin will not cause any problems to the device. when operating at 2mhz and 12v, 2f will work well. at the lowest operating frequency and/or at low input voltages a larger capacitor such as 4.7f is preferred. applications information i load 700ma 300ma v out (ac) 50mv/div i load 700ma 300ma v out (ac) 50mv/div time 20s/div c out = 10f c pl = 0 time 20s/div c out = 10f c pl = 82pf 3509 f11 figure 11. transient load response with different combinations of c out and c pl load current step from 300ma to 700ma r1 = 10k, r2 = 32.4k, v in = 12v, v out = 3.3v, f sw = 2.0mhz
lt3509 18 3509f diode selection the catch diode (d1 from figure 1) conducts current only during switch off time. average forward current in normal operation can be calculated from: iivvv d avg out in out in () ( )/ = the only reason to consider a diode with a larger current rating than necessary for nominal operation is for the worst-case condition of shorted output. the diode current will then increase to the typical peak switch current limit. if transient input voltages exceed 40v, use a schottky diode with a reverse voltage rating of 45v or higher. if the maximum transient input voltage is under 40v, use a schottky diode with a reverse voltage rating greater than the maximum input voltage. table 3 lists several schottky diodes and their manufacturers: table 3. schottky diodes manufacturer/ part number vr (v) iave (a) vf at 1a (mv) on semiconductor mbrm140 40 1 550 microsemi ups140 40 1 450 diodes inc. dfls140l 40 1 550 1n5819hw 40 1 450 short and reverse protection provided the inductors are chosen to not go deep into their saturation region at the maximum i limit current the lt3509 will tolerate a short-circuit on one or both outputs. the excess current in the inductor will be detected by the da comparator and the frequency will reduced until the valley current is below the limit. this shouldnt affect the other channel unless the channel that is shorted is also providing the boost supply to the bd pin. in this case the voltage drop of the other switch will increase and lower the ef? ciency. this could eventually cause the part to reach the thermal shutdown limit. one other important feature of the part that needs to be considered is that there is a parasitic diode in parallel with the power switch. in normal operation this is reverse biased but it could conduct if the load can be powered from an alternate source when the lt3509 has no input. this may occur in battery charging applications or in battery backup systems where a bat- tery or some other supply is diode or-ed with one of the lt3509 regulated outputs. if the sw pin is at more than about 4v the v in pin can attain suf? cient voltage for lt3509 control circuitry to power-up to the quiescent bias level and up to 2ma could be drawn from the backup supply. this can be minimized if some discrete fets or open drain buffers are used to pull down the run/ss pins. of course the gates need to be driven from the standby or battery backed supply. if there is the possibility of a short-circuit at the input or just other parallel circuits connected to v in it would be best to add a protection diode in series with v in . this will also protect against a reversed input polarity. these concepts are illustrated in figure 12. applications information l1 d1 sleep d2 v out c out c boost c in v in 3509 f12 lt3509 gnd v in run/ss1 run/ss2 bd boost sw da figure 12. reverse bias protection
lt3509 19 3509f applications information hot plugging considerations the small size, reliability and low impedance of ceramic capacitors make them attractive for the input capacitor. unfortunately they can be hazardous to semiconductor devices if combined with an inductive supply loop and a fast power transition such as through a mechanical switch or connector. the low-loss ceramic capacitor combined with the just a small amount of wiring inductance forms an underdamped resonant tank circuit and the voltage at the v in pin of the lt3509 can ring to twice the nominal input voltage. see linear technology application note 88 for more details. pcb layout and thermal design the pcb layout is critical to both the electrical and thermal performance of the lt3509. most important is the connec- tion to the exposed pad which provides the main ground connection and also a thermal path for cooling the chip. this must be soldered to a topside copper plane which is also tied to backside and/or internal plane(s) with an array of thermal vias. to obtain the best electrical performance particular at- tention should be paid to keeping the following current paths short: ? the loop from the v in pin through the input capaci- tor back to the ground pad and plane. this sees high di/dt transitions as the power switches turn on an off. excess impedance will degrade the minimum us- able input voltage and could cause crosstalk between channels. ? the loops from the switch pins to the catch diodes and back to the da pins. the fast changing currents and voltage here combined with long pcb traces will cause ringing on the switch pin and may result in unwelcome emi. ? the loop from the regulated outputs through the output capacitor back to the ground plane. excess impedance here will result in excessive ripple at the output. the area of the sw and boost nodes should as small as possible. also the feedback components should be placed as close as possible to the fb pins so that the traces are short and shielded from the sw and boost nodes by the ground planes. figure 13 shows a detail view of a practical board layout showing just the top layer. the complete board is somewhat larger at 7.5cm x 7.5cm. the device has been evaluated on this board in still air running at 700khz switching fre- quency. one channel was set to 5v and the other to 3.3v and both channels were fully loaded to 700ma. the device temperature reached approximately 15?c above ambient for input voltages below 12v. at 24v input it was slightly higher at 17? above ambient. figure 13. sample pcb layout (top layer only)
lt3509 20 3509f 3509 ta03 lt3509 gnd r t sync da1 fb1 run/ss1 da2 fb2 run/ss2 bd v in boost2 boost1 sw2 sw1 15h 0.22f ups140 ups140 0.22f v in = 4.5v to 36v transient to 60v 2.2f 10h v out = 1.8v 0.7a 22f 10k 178k 12.4k 31.6k 22nf 22f 10k 22nf clock 1.6v 0.4v v out = 3.3v 0.7a note: r t chosen for 264khz 1.8v and 3.3v outputs, synchronized to 300khz to 600khz typical applications
lt3509 21 3509f 3509 ta04 lt3509 gnd r t sync da1 fb1 run/ss1 da2 fb2 run/ss2 bd v in boost2 boost1 sw2 sw1 dfls140l dfls140l 10h 0.22f 0.22f 2.2f 6.8h 10f 22nf 10k 40.2k 52.3k 10k 90.9k 10f 0.1f 10k v in = 9.4v to 36v display power control 0v = off 3.3v = on v out = 5v 0.7a v out = 8v 0.7a f sw = 1mhz automotive accessory application 5v logic supply and 8v for lcd display with display power controlled by logic typical applications
lt3509 22 3509f de package 14-lead plastic dfn (4mm 3mm) (reference ltc dwg # 05-08-1708 rev b) 3.00 0.10 (2 sides) 4.00 0.10 (2 sides) note: 1. drawing proposed to be made variation of version (wged-3) in jedec package outline mo-229 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom viewexposed pad 1.70 0.10 0.75 0.05 r = 0.115 typ r = 0.05 typ 3.00 ref 1.70 0.05 1 7 14 8 pin 1 top mark (see note 6) 0.200 ref 0.00 C 0.05 (de14) dfn 0806 rev b pin 1 notch r = 0.20 or 0.35 45 chamfer 3.00 ref recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 2.20 0.05 0.70 0.05 3.60 0.05 package outline 0.25 0.05 0.25 0.05 0.50 bsc 3.30 0.05 3.30 0.10 0.50 bsc package description
lt3509 23 3509f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description mse package 16-lead plastic msop , exposed die pad (reference ltc dwg # 05-08-1667 rev a) msop (mse16) 0608 rev a 0.53 p 0.152 (.021 p .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 C?0.27 (.007 C .011) typ 0.86 (.034) ref 0.50 (.0197) bsc 16 16151413121110 12345678 9 9 1 8 note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.254 (.010) 0 o C 6 o typ detail a detail a gauge plane 5.23 (.206) min 3.20 C 3.45 (.126 C .136) 0.889 p 0.127 (.035 p .005) recommended solder pad layout 0.305 p 0.038 (.0120 p .0015) typ 0.50 (.0197) bsc bottom view of exposed pad option 2.845 p 0.102 (.112 p .004) 2.845 p 0.102 (.112 p .004) 4.039 p 0.102 (.159 p .004) (note 3) 1.651 p 0.102 (.065 p .004) 1.651 p 0.102 (.065 p .004) 0.1016 p 0.0508 (.004 p .002) 3.00 p 0.102 (.118 p .004) (note 4) 0.280 p 0.076 (.011 p .003) ref 4.90 p 0.152 (.193 p .006) detail b detail b corner tail is part of the leadframe feature . for reference only no measurement purpo s 0.12 ref 0.35 ref
lt3509 24 3509f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2007 lt 0109 ? printed in usa related parts part number description comments lt1766 60v, 1.2a (i out ), 200khz, high ef? ciency step-down dc/dc converter v in : 5.5v to 60v, v out : 1.20v, i q = 2.5ma, i sd < 25a, tssop16/e package lt1936 36v, 1.4a (i out ) , 500khz high ef? ciency step-down dc/dc converter v in : 36v to 36v, v out : 1.20v, i q = 1.9ma, i sd < 1a, ms8e package lt1939 25v, 2a, 2.5mhz high ef? ciency dc/dc converter and ldo controller v in : 3.6v to 25v, v out : 0.8v, i q = 2.5a, i sd < 10a, 3mm 3mm dfn-10 lt1976/ lt1977 60v, 1.2a (i out ), 200/500khz, high ef? ciency step-down dc/dc converter with burst mode ? operation v in : 3.3v to 60v, v out : 1.20v, i q = 100a, i sd < 1a, tssop16e package lt3434/ lt3435 60v, 2.4a (i out ), 200/500khz, high ef? ciency step-down dc/dc converter with burst mode operation v in : 3.3v to 60v, v out : 1.20v, i q = 100a, i sd < 1a, tssop16e package lt3437 60v, 400ma (i out ),micropower step-down dc/dc converter with burst mode operation v in : 3.3v to 60v, v out : 1.25v, i q = 100a, i sd < 1a, 3mm 3mm dfn-10, tssop-16e package lt3480 36v with transient protection to 60v, 2a (i out ), 2.4mhz, high ef? ciency step-down dc/dc converter with burst mode operation v in : 3.6v to 38v, v out : 0.78v, i q = 70a, i sd < 1a, 3mm 3mm dfn-10, msop-10e package lt3481 34v with transient protection to 36v, 2a (i out ), 2.8mhz, high ef? ciency step-down dc/dc converter with burst mode operation v in : 3.6v to 34v, v out : 1.26v, i q = 50a, i sd < 1a, 3mm 3mm dfn-10, msop-10e package lt3493 36v, 1.4a(i out ), 750khz high ef? ciency step-down dc/dc converter v in : 36v to 36v, v out : 0.8v, i q = 1.9ma, i sd < 1a, 2mm 3mm dfn-6 package lt3500 36v, 40vmax, 2a, 2.5mhz high ef? ciency dc/dc converter and ldo controller v in : 3.6v to 36v, v out : 0.8v, i q = 2.5ma, i sd < 10a, 3mm 3mm dfn-10 lt3501 25v, dual 3a (i out ), 1.5mhz high ef? ciency step-down dc/dc converter v in : 3.3v to 25v, v out : 0.8v, i q = 3.7ma, i sd = 10a, tssop-20e package lt3505 36v with transient protection to 40v, 1.4a (i out ), 3mhz, high ef? ciency step-down dc/dc converter v in : 3.6v to 34v, v out : 0.78v, i q = 2ma, i sd < 2a, 3mm 3mm dfn-8, msop-8e package lt3506/ lt3506a 25v, dual 1.6a (i out ), 575khz,/1.1mhz high ef? ciency step-down dc/dc converter v in : 3.6v to 25v, v out : 0.8v, i q = 3.8ma, i sd = 30a, 5mm 4mm dfn-16 tssop-16e package lt3507 36v 2.5mhz, triple (2.4a + 1.5a + 1.5a (i out )) with ldo controller high ef? ciency step-down dc/dc converter v in : 4v to 36v, v out : 0.8v, i q = 7ma, i sd = 1a, 5mm 7mm qfn-38 lt3508 36v with transient protection to 40v, dual 1.4a (i out ), 3mhz, high ef? ciency step-down dc/dc converter v in : 3.7v to 37v, v out : 0.8v, i q = 4.6ma, i sd = 1a, 4mm 4mm qfn-24, tssop-16e package lt3510 25v, dual 2a (i out ), 1.5mhz high ef? ciency step-down dc/dc converter v in : 3.3v to 25v, v out : 0.8v, i q = 3.7ma, i sd = 10a, tssop-20e package lt3684 34v with transient protection to 36v, 2a (i out ), 2.8mhz, high ef? ciency step-down dc/dc converter v in : 3.6v to 34v, v out : 1.26v, i q = 850a, i sd < 1a, 3mm 3mm dfn-10, msop-10e package lt3685 36v with transient protection to 60v, 2a (i out ), 2.4mhz, high ef? ciency step-down dc/dc converter v in : 3.6v to 38v, v out : 0.78v, i q = 70a, i sd < 1a, 3mm 3mm dfn-10, msop-10e package burst mode is a trademark of linear technology corporation. 3509 ta02 lt3509 gnd r t sync da1 fb1 run/ss1 da2 fb2 run/ss2 bd v in boost2 boost1 sw2 sw1 mbrm140 mbrm140 4.7h 0.1f 0.1f 2.2f 6.8h v out = 5v 0.7a v out = 3.3v 0.7a 10f 22nf 10k 16.9k 52.3k 31.6k 10f 22nf 10k v in = 6.5v to 16v transient to 60v f sw = 2mhz 2mhz, 5v and 3.3v outputs typical applications

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